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Merge branch 'master' of https://verag.visualstudio.com/SDL/_git/SDL

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This commit is contained in:
Andreas Luxbauer
2024-01-23 07:55:35 +01:00
parent 4acf2f9050 8f06e48af9
commit 5d7e95eb05
3 changed files with 13 additions and 9 deletions
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8
SDL/SDL.vbproj
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@@ -42,8 +42,10 @@
<DefineTrace>true</DefineTrace> <DefineTrace>true</DefineTrace>
<OutputPath>bin\Debug\</OutputPath> <OutputPath>bin\Debug\</OutputPath>
<DocumentationFile>SDL.xml</DocumentationFile> <DocumentationFile>SDL.xml</DocumentationFile>
<NoWarn>42016,41999,42017,42018,42019,42032,42036,42020,42021,42022</NoWarn> <NoWarn>41999,42016,42017,42018,42019,42020,42021,42022,42032,42036</NoWarn>
<Prefer32Bit>false</Prefer32Bit> <Prefer32Bit>false</Prefer32Bit>
<WarningsAsErrors>
</WarningsAsErrors>
</PropertyGroup> </PropertyGroup>
<PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Release|AnyCPU' "> <PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Release|AnyCPU' ">
<PlatformTarget>AnyCPU</PlatformTarget> <PlatformTarget>AnyCPU</PlatformTarget>
@@ -53,8 +55,10 @@
<Optimize>true</Optimize> <Optimize>true</Optimize>
<OutputPath>bin\Release\</OutputPath> <OutputPath>bin\Release\</OutputPath>
<DocumentationFile>SDL.xml</DocumentationFile> <DocumentationFile>SDL.xml</DocumentationFile>
<NoWarn>42016,41999,42017,42018,42019,42032,42036,42020,42021,42022</NoWarn> <NoWarn>41999,42016,42017,42018,42019,42020,42021,42022,42032,42036</NoWarn>
<Prefer32Bit>false</Prefer32Bit> <Prefer32Bit>false</Prefer32Bit>
<WarningsAsErrors>
</WarningsAsErrors>
</PropertyGroup> </PropertyGroup>
<PropertyGroup> <PropertyGroup>
<OptionExplicit>On</OptionExplicit> <OptionExplicit>On</OptionExplicit>

2
VERAG_PROG_ALLGEMEIN/Mitarbeiterverzeichnis/frmMitarbeitersuche.vb
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@@ -331,7 +331,7 @@ Public Class frmMitarbeitersuche
If VERAG_PROG_ALLGEMEIN.cAllgemein.MITARBEITER.mit_niederlassung <> "" Then If VERAG_PROG_ALLGEMEIN.cAllgemein.MITARBEITER.mit_niederlassung <> "" Then
Select Case VERAG_PROG_ALLGEMEIN.cAllgemein.NIEDERLASSUNG Select Case VERAG_PROG_ALLGEMEIN.cAllgemein.NIEDERLASSUNG
Case "SUB" : timestp = timestp.AddHours(1) Case "SUB" : timestp = timestp.AddHours(1)
Case "SBG" : timestp = timestp.AddHours(1) '? 30 Case "SBG" : timestp = timestp.AddHours(1) 'Verag Post + AT Zoll
Case "WAI" : timestp = timestp.AddMinutes(30) Case "WAI" : timestp = timestp.AddMinutes(30)
Case "NKD" : timestp = timestp.AddMinutes(20) Case "NKD" : timestp = timestp.AddMinutes(20)
Case "DTB" : timestp = timestp.AddMinutes(30) Case "DTB" : timestp = timestp.AddMinutes(30)

2
VERAG_PROG_ALLGEMEIN/VERAG_PROG_ALLGEMEIN.vbproj
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@@ -16,7 +16,7 @@
<TargetFrameworkProfile /> <TargetFrameworkProfile />
</PropertyGroup> </PropertyGroup>
<PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Debug|AnyCPU' "> <PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Debug|AnyCPU' ">
<PlatformTarget>x64</PlatformTarget> <PlatformTarget>AnyCPU</PlatformTarget>
<DebugSymbols>true</DebugSymbols> <DebugSymbols>true</DebugSymbols>
<DebugType>full</DebugType> <DebugType>full</DebugType>
<DefineDebug>true</DefineDebug> <DefineDebug>true</DefineDebug>